As the data processing speed of systems has increased, DRAM semiconductor devices may become a “bottleneck” for data flow in the system. Accordingly, DRAM latency may be an importance factor in the data processing speed of the system. An asynchronous DRAM semiconductor device includes a delay time for synchronizing signals with a system clock. Signals of a SDRAM semiconductor device are synchronized with a system bus clock.
The SDRAM semiconductor device represents a DRAM semiconductor device that follows the SDRAM standard decided by JEDEC (Joint Electron Device Engineering Council). The following represents some features of the SDRAM semiconductor device:
1) input circuit/output circuit synchronized with an external clock signal
2) burst access
3) structure of a multi-bank
4) memory access based on commands
5) data path using pipeline method, etc.
Timing parameters of the SDRAM semiconductor device have values corresponding to integer number of clock signals so as to implement the input circuit/output circuit that are synchronized with the external clock. In addition, when a control signal is inputted to the SDRAM semiconductor device, the control signal is maintained and is not changed if an internal register is not updated since the control signal is stored in the internal register. A clock signal and another control signal are changed to change the inputted control signal. An operation status of the SDRAM semiconductor device may be determined by combination of at least one control signal. A command decoder of the SDRAM semiconductor device decodes the at least one control signal so that the SDRAM semiconductor device starts various operations based on the decoding result.
The control signal is referred to as a command since the change of the inputted control signal and the start of the operation of the SDRAM semiconductor device is similar to programming operation. A burst access represents that input or output of data in a memory device is synchronized with a clock signal so that data are successively inputted to or outputted from the memory device. When an activation command and a row address is applied to the memory device at the moment of a rising edge of the clock signal, the memory device has an activated state and a corresponding word line is selected by the row address. When a read command and a column address are inputted to the memory device in response to subsequent clock signal, the burst access begins. In other words, the inputted column address increases by one after subsequent clock signals, and data are successively outputted from the memory device.
A bank represents a memory cell group that may independently operate so as to support high speed operation through interleaving in a memory module. The memory cells in a bank share a data bus, address line and a control signal line, etc., and may independently operate from other banks. Thus, when a read operation is performed in a bank, a refresh operation or a word line selection by the row address may be performed in other bank.
In a pipeline method, flip-flop or latch divides a data path so that a plurality of circuit blocks may operate simultaneously. In other words, at least one flip-flop or at least one latch is disposed on the data path, so that the data path is divided into a plurality of data path respectively including at least one circuit block. Thus, while data read from a circuit block are latched and are outputted to an external source, a new address may be inputted to the memory device via another data path or a pre-charge operation may be performed via another data path.
In a Dual Data Rate (DDR) SDRAM, data or command are synchronized with a rising edge of a clock signal and a falling edge of the clock signal. Thus, double data rate operation of about 200 MHz may be obtained using a 100 MHz clock signal. A duty cycle of the clock signal has 50% so as to obtain the double data rate. DDR SDRAMs may operate in DDR1 mode or DDR2 mode. In a DDR1 SDRAM, 2 bits are pre-fetched during data input/output operation so that a burst length of data is 2. In the DDR2 SDRAM, 4 bits are pre-fetched during data input/output operation so that the burst length of data is 4. Two consecutive data synchronized with a clock signal are successively transferred via an input (or output) terminal when the burst length of data is 2. Four consecutive data synchronized with a clock signal are successively transferred via an input (or output) terminal when the burst length of data is 4.
The operation of a DDR1 compliant SDRAM may not be compatible with the operation of a DDR2 compliant SDRAM since the DDR1 SDRAM is manufactured to have circuit structures different from that of DDR2 SDRAM. Therefore, it may be difficult to implement a system using DDR1 and DDR2 compliant SDRAMs.